Multi-bit time delay adjuster unit for high rf applications and method

ABSTRACT

In the present invention a multi-bit time-delay adjuster using Radio Frequency (RF) MicroElectroMechanical (MEM) switches is disclosed for applications in MCPAs with feed-forward linearization technique. The MEM switching system used in the multi-bit time-delay adjuster makes it possible to automatic control the time-delay match with very high precision required in feed-forward MultiCarrier Power Amplifiers (MCPA), instead of a manual trimming process. A searching process suitable for the automatic control of time-delay match is also introduced and demonstrated by an example of a four-bit time-delay adjuster.

FIELD OF INVENTION

[0001] The present invention relates to a method for adjusting atime-delay using a multi-bit time-delay adjuster unit and a multi-bittime-delay adjuster unit according to the preamble of the independentclaims.

[0002] The method and the time-delay adjuster unit are speciallysuitable for high precision time-delay matches required in e.g. aMultiCarrier Power Amplifier (MCPA).

BACKGROUND OF THE INVENTION

[0003] Highly linear and efficient RF power amplifiers are criticalcomponents in modern radio communications systems. Feed-forwardlinearization is a known linearization technique, which is especiallyused in MCPAs in order to fulfill extremely high linearity requirements,e.g. for third generation (3G) radio communication systems using high RFfrequencies in the order of GHz. It is difficult to implementcost-effective and time-efficient feed-forward linearization techniquedue to stringent requirements for accurate match of the time-delay loopsin the MCPAs. Because of common deviations of RF components fabricatedin standard processes, the accurate time-delay match in the MCPAs withfeed-forward linearization implementation is today made manually by e.g.cutting or soldering the length of delay-line cables or microstriplines,which is a time-consuming and a costly process. Such a manual testingprocess may often lead to lower linearity performance of the MCPAs dueto limited manual capability of making extremely fine tuning match,especially in mass production. Besides, when the MCPAs in fields aredeployed with radio base stations, they have to be regularly tested andpossibly re-configured in order to compensate variations in thecharacteristics of the MCPAs due to component aging as well asenvironmental effects. This is a difficult task for mobile telephoneoperators who may have no specially trained technicians.

[0004] In spite of ideas of introducing tunable delay lines forfeed-forward power amplifiers, and thus obtaining the possibility toimplement an automatic time-delay adjusting method, there are practicaldifficulties due to e.g. the extremely high linearity requirements forthe feed-forward MCPAs. That prevents the use of existing semiconductortunable components. Ideas of using delay filters to replace conventionaltransmission delay lines, such as coaxial cables, have also beenproposed, which may provide size, integration, and possible costadvantages. There are however some practical problems with regard toe.g. the bandwidth limitation of the delay filter. The intrinsiclinearity characteristic and the time-delay tunability of the delayfilter in a relatively wide tuning range required by the feed-forwardMCPAs are examples of such problems.

[0005] The U.S. Pat. No. 6,281,838 discloses a phased array antennasystem that employs Single-Pole Single Through (SPST) RF MEM switchesand transmission lines to provide true time-delays in order to steer theantenna beam. However, the antenna system described in U.S. Pat. No.6,281,838 does not provide an automatic time-delay adjustment and inparticular not in connection with MCPA.

[0006] The U.S. Pat. No. 5,828,699 A discloses an adaptive time-delayadjuster. The time-delay elements is always connected to thetransmission line path (see FIG. 1) even when the time-delay elementsare switched off. That will affect the local impedance and RFcharacteristics of the entire delay line, which results in localimpedance mismatching, reflection, and that certain filter functionsblock certain bands of signals passing through the delay line. Thus, thetime-delay adjuster disclosed in U.S. Pat. No. 5,828,699 is not adaptedfor high RF frequencies.

[0007] Thus, the object of the present invention is to achieve a methodfor automatic time-delay adjustment with a high precision for use inhigh frequency applications, and also a time-delay adjuster unit for usein high frequency applications when implementing the method.

SUMMARY

[0008] The above-mentioned object is achieved by the present inventionaccording to the independent claims by a method having the features ofclaim 1 and by a time-delay adjuster unit having the features of claim9.

[0009] Preferred embodiments are set forth in the dependent claims.

[0010] An advantage with the present invention is that extremely highprecision of the time delay adjuster can be achieved in a short time.

[0011] Another advantage with the present invention is that it makes itpossible for remote control/adjustment of feedforward MCPAs that isparticularly useful for mobile telecom operators.

[0012] Yet another advantage with the present invention is that itfacilitates mass production of feedforward MCPAs with low cost and highperformance by avoiding both time and labor cost consuming manualtrimming processes.

[0013] A further advantage with the present invention is obtained inaccordance with preferred embodiment by using RF MEM switches. Thetime-delay adjuster unit then obtains desired properties, required bythe feedforward MCPAs, such as high linearity, low insertion loss andcapability of broadband operations.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1a shows a one-bit time-delay adjuster as an illustrativeexample of prior art. b shows a two-bit time-delay adjuster as anillustrative example of prior art.

[0015]FIG. 2 shows a typical feed-forward final-stage power amplifierblock diagram according to prior art.

[0016]FIG. 3 shows a five two-bit time-delay adjuster unit according tothe present invention.

[0017]FIG. 4 discloses a four-bit time-delay adjuster unit according toa first preferred embodiment the present invention.

[0018]FIG. 5 shows a scheme of the division of the total adjustabletime-delay implemented in a multi-bit time-delay adjuster unit accordingto the present invention.

[0019]FIG. 6 shows a flowchart describing the auto-search methodaccording to the present invention.

[0020]FIG. 7 shows a flowchart describing an auto-search method in ageneral mode according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0021] A method for adjusting a time-delay using a multi-bit time-delayadjuster unit for automatic tuning of any specific time-delay within atunable time-delay interval specified for the time-delay adjuster unitwill be described below in the detailed description of the presentinvention. This tuning is e.g. required in a MCPAs with feed-forwardlinearization technique

[0022] In accordance with the present invention, a multi-bit time-delayadjuster unit for automatic adjusting a time-delay with a high precisionis disclosed. The adjuster unit described in the examples below,comprises MicroElectroMechanical (MEM) switches and in particular, RFMEM Single-Pole Double Through (SPDT) switches. The invention is notlimited to the use of RF MEM switches, it is also possible to use othertypes of switches. However, RF MEM SPDT switches are specially designedfor digital tuning of time-delay matching required in e.g. feed-forwardloops in MCPAs. RF MEM switches may also be used because the RF MEMswitches have superior linearity performance, broadband frequencyresponse, and much lower insertion loss than their semiconductorcounterparts. These features are known to a man skilled in the art to beof particularly importance in feed-forward MCPAs.

[0023] Both FIG. 1a and FIG. 1b show illustrative examples of time-delayadjusters according to the prior art. FIG. 1a, shows a one-bittime-delay adjuster and FIG. 1b shows a two-bit time-delay adjuster.S_(i)(i=1, 2, 3, 4) denotes the MEM switches, and l, l₁, l₂ denote thelengths of the delay line elements, which e.g. may be microstriplines.It is shown that the one-bit time-delay adjuster may have two differenttime-delay states, and the two-bit time-delay adjuster may have fourdifferent time-delay states. In accordance with FIGS. 1a and 1 b, thedelay line elements are disconnected when they are switched off. Ingeneral, an n-bit time-delay adjuster has 2^(n) different time-delaystates.

Multi-Bit Time-Delay Adjuster Unit

[0024] In the present invention a multi-bit time-delay adjuster unit,using RF MEM SPDT switches specially designed for time-delay adjustmentin high RF frequency applications, e.g. a feed-forward loop in a MCPA,is considered. A typical scheme of a feed-forward final stage MCPA isdisclosed in FIG. 2.

[0025] The multi-bit time-delay adjuster units as described in thepresent invention may replace the two time-delay adjustor units.Provided that both the time-delay adjusters shown in FIG. 2 is low RFpower devices it is possible to use RF MEM switches that currently havelimited power handling capability (i.e. less than a few Watts).

[0026] A multi-bit time-delay adjuster, comprising a total digitallytunable delay time interval T, that is divided according to the presentinvention, provides a high precision time-delay adjuster unit, thatcomprises a relative few number of bits (in the preferred embodimentfour bits). A high-bit e.g. ten-bit time-delay adjuster may be producedin practice, but its RF performance will be generally worse than itslower-bit counterpart. In addition, the size and cost of said high-bittime-delay adjuster would be tremendously high. The number of bits isreferred to in the meaning of the number of switching states. I.e. an mbit adjuster has 2^(m) different switching states. The four-bittime-delay adjuster according to the preferred embodiment is implementedwith RF MEM SPDT switches, instead of the Single-Pole Single Through(SPST) switches used in U.S. Pat. No. 6,281,838 The RF MEM SPDT switchesshown in a first preferred embodiment of the present invention in FIG. 4have the advantage of less stiction problems than RF MEM SPST switchesthat may cause failure of the adjustable delay-lines due to the use ofbi-directional force actuation. In addition, the SPDT switches shown inFIG. 4 reduce the number of switch elements used in the adjustable delayline.

[0027]FIG. 4 shows further a five level division of the four-bittime-delay adjuster unit, in which the time-delay elements can bedefined as follows. Suppose that the specified total time delay is T. Azero time-delay of the adjuster is defined as the case when l₁₁, l₂₁,l₃₁, l₄₁, and l₅₁ are connected, i.e. switched on. The time-delayelements are always disconnected when they are switched off. Thatimplies that the present invention is suitable for high RF frequencyapplications in accordance with the discussion above In the backgroundsection. In this embodiment, two RF MEM switches, (e.g. the switch withthe delay element l₁₄ and l₁₃ is connected in parallel with the switchwith the delay element l₁₂ and l₁₁), are connected in parallel and eachset of parallel RF MEM switches are then connected in serial. Theindividual time-delay elements in FIG. 4 are defined by the examplebelow according to the division disclosed in the present invention,which is suitable for fine tuning match used in e.g. feedforward MCPAs.

[0028] At a First Level Division:

[0029] l₁₂ is made in such a way that a time-delay of T/4 is obtainedwhen l₁₂, l₂₁, l₃₁, l₄₁, and l₅₁ are connected.

[0030] l₁₃ is made in such a way that a time-delay of 2T/4 is obtainedwhen l₁₃, l₁₂, l₂₁, l₄₁, and l₅₁, are connected.

[0031] l₁₄ is made in such a way that a time-delay of 3T/4 is obtainedwhen l₁₄, l₂₁, l₃₁, l₄₁, and l₅₁ are connected.

[0032] At a Second Level Division:

[0033] l₂₂ is made in such a way that a time-delay of T/4² is obtainedwhen l₁₁, l₂₂, l₃₁, l₄₁, and l₅₁, are connected.

[0034] l₂₃ is made in such a way that a time-delay of 2T/4² is obtainedwhen l₁₁, l₂₃, l₃₁, l₄₁, and l₅₁, are connected.

[0035] l₂₄ is made in such a way that a time-delay of 3T/4² is obtainedwhen l₁₁, l₂₄, l₃₁, l₄₁, and l₅₁ are connected.

[0036] At the Third Level Division:

[0037] l₃₂ is made in such a way that a time-delay of T/4³ is obtainedwhen l₁₁, l₂₁, l₃₂, l₄₁, and l₅₁ are connected.

[0038] l₃₃ is made in such a way that a time-delay of 2T/4³ is obtainedwhen l₁₁, l₂₁, l₃₃, l₄₁, and l₅₁ are connected.

[0039] l₃₄ is made in such a way that a time-delay of 3T/4³ is obtainedwhen l₁₁, l₂₁, l₃₄, l₄₁, and l₅₁ are connected.

[0040] At the Fourth Level Division:

[0041] l₄₂ is made in such a way that a time-delay of T/4⁴ is obtainedwhen l₁₁, l₂₁, l₃₁, l₄₂, and l₅₁ are connected.

[0042] l₄₃ is made in such a way that a time-delay of 2T/4⁴ is obtainedwhen l₁₁, l₂₁, l₃₁, l₄₃, and l₅₁ are connected.

[0043] l₄₄ is made in such a way that one gets a time-delay of 3T/4⁴when l₁₁, l₂₁, l₃₁, l₄₄, and l₅₁ are connected.

[0044] At the Fifth Level Division:

[0045] l₅₂ is made in such a way that a time-delay of T/4⁵ is obtainedwhen l₁₁, l₂₁, l₃₁, l₄₁, and l₅₂ are connected.

[0046] l₅₃ is made in such a way that a time-delay of 2T/4⁵ is obtainedwhen l₁₁, l₂₁, l₃₁, l₄₁, and l₅₃ are connected.

[0047] l₅₄ is made in such a way that a time-delay of 3T/4⁵ is obtainedwhen l₁₁, l₂₁, l₃₁, l₄₁, and l₅₄ are connected.

[0048] By such a way of division, the longest time-delay is the casewhen l₁₄, l₂₄, l₃₄, l₄₄, and l₅₄ are connected, which corresponds to atotal time-delay of T-T/4⁵. T/4⁵ is the finest precision (if T=10 ns,T/4⁵=9.76 ps) achievable by the time-delay adjuster for the adjustabletime-delay range of 0 to 10 ns according to the design given above.

[0049] In FIG. 5, it is disclosed how the tunable time-delay interval[0,T] is divided up to the fifth level division. The method used for thedivision is illustrated in the example below.

[0050] 1. The time-delay interval [0,T] is specified.

[0051] 2. The first level division: The time-delay T is divided intofour equal segments. It may also be divided into another number of equalsegments, however four is preferred since it makes it possible to use acombination of standard two-bit time-delay adjusters and/or to use aspecific type of RF MEM switches as shown in FIG. 4. Here, in the caseof four equal segments, each segment has a time-delay of T/4 (if T=10ns, T/4=2.5 ns for each time-delay segment).

[0052] 3. The second level division: The last segment, (it is naturallypossible to use any other segment) of the first level division isfurther divided into four smaller equal time-delay segments. I.e., eachsegment has a time-delay of (T/4)/4 (if T=10 ns, (T/4)/4=0.625 ns).

[0053] 4. The third level division: The last segment of the second leveldivision is further divided into four smaller equal time-delay segments.I.e., each segment has a time-delay of (T/16)/4 (if T=10 ns,(T/16)/4=0.15625 ns).

[0054] 5. The fourth level division: The last segment of the third leveldivision is then further divided into four smaller equal time-delaysegments. I.e., each segment has a time-delay of (T/64)/4 (if T=10 ns,(T/64)/4=0.039 ns).

[0055] 6. The fifth level division: The last segment of the fourth leveldivision is further divided into 4 smaller equal time-delay segments,i.e., each segment has a time-delay of (T/256)/4 (if T=10 ns,(T/256)/4=0.00976 ns). It is here shown that 9.76 ps precision oftime-delay adjustment can be achieved by a four-bit time-delay adjusterwith sixteen different time-delay states.

[0056] If a 5-bit time-delay adjuster with 32 different time-delaystates designed according to the method above is used, a precision of9.2 fs may be achieved at fine-tuning of the time-delay; Assuming thatthe signal propagation speed in the delay line is v_(s)=10⁸ m/s, the 9.2fs time-delay would correspond to a length of the delay line segment ofabout 0.92 μm, which is hardly achievable by manual adjustment by, e.g.,cutting or soldering the delay line.

[0057] The number of the required divisions depends on the total maximumtime-delay required and the time-delay precision specified in practicalapplications.

[0058] The time delay adjuster unit comprises segments of transmissionlines of different lengths connected by MEM switches. In general, thereare a number of ways of physically constructing time delay adjusters.E.g., besides the mentioned integrated multi-bit time-delay adjusterunit, it is also possible to use a combination of low-bit time-delayadjusters. An example of such a combination of five two-bit time-delayadjusters, which can either be in a properly packaged form, orfabricated on an integrated circuit, is shown in FIG. 3. The time-delayadjuster unit may use the search algorithm, introduced below, where itcan reach the time-delay match within a precision of 8 ps by means of a10 ns tunable time-delay interval T disclosed in FIG. 5.

[0059] All switches in the time-delay adjusters are controlled byelectronic circuits, which are programmable by means of computer programproduct. The computer program product comprises the software code meansfor performing the steps of the method described above. The computerprogram product is run on processing means in a computer or in anotherlogic control unit. The computer program is loaded directly or from acomputer usable medium, such as a floppy disc, a CD, the Internet etc.

Automatic Time-Delay Search Method

[0060] In order to use the above-disclosed multi-bit time-delay adjusterunit for e.g. feed-forward MCPAs, an automatic search method for thebest time-delay match is disclosed below in accordance with the presentinvention. The search method is described by the example below and isillustrated in a flowchart in FIG. 6.

[0061] A Control parameter Cp is introduced as a measure of a relationbetween a present time-delay and a desired time-delay. The Cp is setaccording to the performance, e.g. linearization requirement, of theMCPA during a test of the time-delay adjustment.

[0062] The control parameter Cp may take the following exemplary values:

[0063] C_(p)>0, e.g. Cp=1: The time-delay of the time-delay adjustershould be increased.

[0064] C_(p)<0, e.g. Cp=−1: The time-delay of the time-delay adjustershould be decreased.

[0065] C_(p)=0: Match is reached.

[0066] In practice, the perfect match is seldom reached. Instead, thematch is considered to be reached (Cp=0) if the time-delay of theadjuster unit is within a specified precision range Tp. The precisionrange Tp is determined by the time-delay adjuster unit. E.g., for thefour-bit time-delay adjuster designed above with a time-delay intervalof 10 ns, the precision range Tp is 9,76 ps, which is the smallesttime-delay segment available in the above mentioned four-bit time-delayadjuster, while for the five-bit time-delay adjuster, Tp is 9.2 fs.

[0067] Considering now an example of the above mentioned four-bittime-delay adjuster unit having the 10 ns tuning range (i.e. the totaltime-delay interval T). Suppose that the desired time-delay match willbe achieved at 6.35 ns. The following time-delay segments for thefour-bit time-delay adjuster at five level divisions are introduced:

[0068] ΔT(1)=2.5 ns denotes the first level time-delay segment.

[0069] ΔT(2)=0.625 ns denotes the second level time-delay segment.

[0070] ΔT(3)=0.156 ns denotes the third level time-delay segment.

[0071] ΔT(4)=0.039 ns denotes the fourth level time-delay segment.

[0072] ΔT(5)=0.00976 ns denotes the fifth level time-delay segment.

[0073] ΔT(k)=T/n^(k) T is here 10 ns, n=4 and k is an integer numberfrom 1 to p and here is p=5.

[0074] The number of level divisions, referred to as p, is set by thetime-delay adjuster (hardware) used in the system. The proper choice ofthe time delay adjuster depends e.g. on the specification of the MCPAs.

[0075] An auto-search process starts, when the initial settings of theadjustable time-delay line are performed: p0 1. First, set thetime-delay of the time-delay adjuster to: T_(d)(1)=ΔT(1)=2.5 ns;

[0076] System performance test sets C_(p)(1)>0 (since T_(d)(1)=2.5ns<6.35 ns, the desired value);

[0077] 2. Since C_(p)(1)>0, set T_(d)(2)=T_(d)(1)+ΔT(1)=5 ns;

[0078] System performance test sets C_(p)(2)>0 (since the time-delaysegment sum Td(2)=5 ns<6.35 ns);

[0079] 3. Since C_(p)(2)>0, set T_(d)(3)=T_(d)(2)+ΔT(1)=7.5 ns;

[0080] System performance test sets now C_(p)(3)<0 (since T_(d)(3)=7.5ns>6.35 ns);

[0081] 4. Since C_(p)(3)<0, while C_(p)(2)>0, we setT_(d)(4)=T_(d)(2)+ΔT(2)=5.625 ns (T_(d)(3) and ΔT(1) are too long,therefore T_(d)(2) and ΔT(2) are used.)

[0082] System performance test will now set C_(p)(4)>0 (sinceT_(d)(4)=5.625 ns<6.35 ns);

[0083] 5. Since C_(p)(4)>0, while C_(p)(3)<0, we setT_(d)(5)=T_(d)(4)+ΔT(2)=6.25 ns;

[0084] System performance test will now set C_(p)(5)>0 (sinceT_(d)(5)=6.25 ns<6.35 ns);

[0085] 6. Since C_(p)(5)>0, and C_(p)(4)>0, we setT_(d)(6)=T_(d)(5)+ΔT(2)=6.875 ns;

[0086] System performance test will now set C_(p)(6)<0 (sinceT_(d)(6)=6.875 ns>6.35 ns);

[0087] 7. Since C_(p)(6)<0, while C_(p)(5)>0, we setT_(d)(7)=T_(d)(5)+ΔT(3)=6.406 ns;

[0088] System performance test will now set Cp(7)<0 (since Td(7)=6.406ns >6.35 ns);

[0089] 8. Since C_(p)(7)<0, while C_(p)(6)<0, we setT_(d)(8)=T_(d)(5)+ΔT(4)=6.289 ns;

[0090] System performance test will now set C_(p)(8)>0 (sinceT_(d)(8)=6.289 ns<6.35 ns);

[0091] 9. Since C_(p)(8)>0, and C_(p)(7)>0, we setT_(d)(9)=T_(d)(8)+ΔT(4)=6.328 ns;

[0092] System performance test will now set C_(p)(9)>0 (sinceT_(d)(9)=6.328 ns<6.35 ns);

[0093] 10. Since C_(p)(9)>0, and C_(p)(8)>0, we setT_(d)(10)=T_(d)(9)+ΔT(4)=6.367 ns;

[0094] System performance test will now set C_(p)(10)<0 (sinceTd(10)=6.367 ns>6.35 ns);

[0095] 11. Since C_(p)(10)<0, while C_(p)(9)>0, we setT_(d)(11)=T_(d)(9)+ΔT(5)=6.33776 ns;

[0096] System performance test will now set C_(p)(11)>0 (sinceT_(d)(11)=6.33776 ns<6.35 ns);

[0097]12. Since C_(p)(11)>0, while C_(p)(10)<0, we setT_(d)(12)=T_(d)(11)+ΔT(5)=6.34752 ns;

[0098] Since |T_(d)(12)−6.35|=0.00248 ns, which is within the precisionrange of 0.00976 ns set by the multi-bit time-delay adjuster shown inFIG. 4, the search process is stopped i.e., by setting Cp(12)=0.

[0099] This example shows that after only 12 search steps, thetime-delay match within the precision range of 9.76 ps can be reached.The precision is hence limited by the four-bit time-delay adjuster unit.The demonstrated searching process may be generalized to other multi-bittime-delay adjusters and can be programmed as an automatic searchalgorithm for specific system applications when the RF MEM switchesinside the multi-bit time-delay adjuster is electronically controlled bydigital circuits.

[0100]FIG. 7 shows a flowchart of a method according to the presentinvention. The method is performed by means of a multi-bit time-delayadjuster and is intended for automatic control of the time-delay matche.g. required in feedforward MCPAs. The method comprises the followingsteps:

[0101]701. The total number of level divisions p is defined.

[0102]702. A time-delay segment ΔT(k) is defined for each level k, wherek is an integer number from 1 to p.

[0103]703. A Control parameter Cp is set where Cp is a measure of therelation between a present time-delay and a desired time-delay.

[0104]704. A time-delay segment sum is determined by addition oftime-delay segments ΔT(k).

[0105]705. Steps 703 and 704 are repeated until the desired time-delayis reached or the sum is within an allowed precision range Tp and Cp isgiven a predetermined value, e.g. Cp=0.

[0106] Generally, the above-described method according to the presentinvention may be used not only for feed-forward MCPAs, but also forother applications, where precise control of the phase or the time-delayof signals is required, such as adaptive antennas.

[0107] The method is implemented by means of a computer program productcomprising the software code means for performing the steps of themethod. The computer program product is run on processing means in acomputer or in any other logical control unit. The computer program isloaded directly or from a computer usable medium, such as a floppy disc,a CD, the Internet etc.

[0108] The present invention is not limited to the above-describedpreferred embodiments. Various alternatives, modifications andequivalents may be used. Therefore, the above embodiments should not betaken as limiting the scope of the invention, which is defined by theappending claims.

1. A method for adjusting a time-delay for a high RF frequencyapplication using a multi-bit time-delay adjuster unit, wherein the unithaving a tunable time-delay within a specified time-delay interval[0,T], and being adapted to reach a desired time-delay, wherein themethod comprises: defining a total number of level divisions p, definingfor each level division a time-delay segment ΔT(k), where k is aninteger number from 1 to p, setting a Control parameter Cp, wherein Cpbeing a measure of a relation between a present time-delay and thedesired time-delay, determining a time-delay segment sum by addingtime-delay segments ΔT(k), repeating the setting step and thedetermining step until the desired time-delay is reached or the sum iswithin an allowed precision range Tp, and Cp is then given apredetermined value, e.g. Cp=0.
 2. The method according to claim 1,wherein the value of Cp is depending on whether the desired time-delayis greater than, smaller than or equal to the present time-delay.
 3. Themethod according to claim 1, wherein the setting-step further comprises:controlling whether the sum is to be increased or the sum is to bedecreased.
 4. The method according to claim 1, wherein the time-delaysegments, ΔT(k) are defined by the following steps: specifying thetunable time-delay interval [0,T], determining the number of leveldivisions p, repeatedly performing p (p>1) level divisions wherein atime-delay segment ΔT(k) is further divided into n equal time-delaysegments ΔT(k+1) on a lower level.
 5. The method according to claim 1,wherein the switches are Radio Frequency (RF) MicroElectroMechanical(MEM) switches.
 6. The method according to claim 1, wherein the switchesare Single-Pole Double Through (SPDT) RF MEM switches.
 7. The methodaccording to claim 1, wherein the size of each time-delay segment ΔT(k)is T/n^(k), where k is an integer number from 1 to p, T denotes thelength of the specified time-delay interval and n denotes the number oftime-delay segments that the time-delay interval T is divided into 8.The method according to claim 1, wherein the total number of leveldivisions is depending of the number of available states of thetime-delay adjuster unit.
 9. The method according to claim 7, wherein nequals four.
 10. The method according to claim 1, wherein the adjustabletime-delay is adjusted for MultiCarrier Power Amplifier (MCPA) withfeed-forward linearization technique.
 11. A computer program productstored on a computer usable medium, comprising a readable program forcausing a processing means in a computer or in any other logical controlunit, to control the execution of the steps in claim
 1. 12. A computerprogram product directly loadable into a computer usable medium,comprising the software code portions for performing the steps claim 1.13. A multi-bit time-delay adjuster unit for high RF frequencyapplications adapted to tune a time-delay within a specified time-delayinterval [0,T], wherein the unit comprises switches, wherein said unitcomprises level divisions means adapted to repeatedly perform p leveldivisions (p>1) in order to provide time-delay segments ΔT(k) accordingto the method defined by claim
 1. 14. The multi-bit time-delay adjusteraccording to claim 13, wherein the switches are Radio Frequency (RF)MicroElectroMechanical (MEM) switches.
 15. The multi-bit time-delayadjuster according to claim 14, wherein the RF MEM switches areSingle-Pole Double Through (SPDT) RF MEM switches.
 16. The multi-bittime-delay adjuster unit according to wherein the size of eachtime-delay segment ΔT(k) is of T/n^(k), where T denotes the specifiedtime-delay interval, n denotes the number of segments that thetime-delay interval T is divided into, and k is an integer number from 1to p, where p is the total number of level divisions.
 17. The multi-bittime-delay adjuster unit according to claim 13, wherein the total numberof level divisions is depending of the number of available states of thetime-delay adjuster unit.
 18. The multi-bit time-delay adjuster unitaccording to claim 16, wherein n equals four.
 19. The multi-bittime-delay adjuster unit according to claim 13, wherein the adjustabletime-delay is adjusted for MultiCarrier Power Amplifier (MCPA) withfeed-forward linearization technique.